r8a66161dd/sp 16-bit led driver with shift register and latch rej03f0262-0100 rev.1.00 jan.16.2008 page 1 of 7 rej03f0262-0100 rev. 1.00 jan. 16. 2008 description r8a66161 is a led array driver having a 16-bit serial input and parallel output shift register function with direct coupled reset input and output latch function. this product guarantees the output current of 24ma (vcc =5v case) which is sufficient for anode common led drive, capable of following 16-bits continuously at the same time. parallel output is open drain output. in addition, as this product has been designed in complete cmos, power consumption can be greatly reduced when compared with conventional bipolar or bi-cmos products. furthermore, pin layout ensures the realization of an easy printed circuit. r8 a66161 is the succession product of m66311. features anode common led drive v cc 5v or 3.3v single power supply high output current: all parallel outputs q a~ q p i ol =24ma (at v cc =5.0v) i ol =12ma (at v cc =3.3v) simultaneous lighting available low power dissipation: 100uw/package (max) (v cc =5.0v, ta=25 ? , quiescent state) high noise margin: schmitt input circuit provides responsiveness to a long line length equipped with direct-coupled reset open drain output: (except serial data output sq p ) wide operating temperature range: ta=-40 o c~+85 o c pin layout facilitates printed circuit wiring. (this la yout facilitates cascade co nnection and le d connection) application led array drive, the various led display modules ppc, printer, vcr, mini-compo, button-telephone etc. all of led display equipment block diagram a serial data input ck s shift clock input ck l latch clock input r direct reset input serial data output parallel data outputs logic diagram serial data output sq p output format parallel data outputs q a ? q p data signal oe signal 12 q ck d s q ck d s q p 11 q ck d s q ck d s q o 13 q ck d s q ck d s q n 14 q ck d s q ck d s q m 15 q ck d s q ck d s q l 16 q ck d s q ck d s q k 17 q ck d s q ck d s q j 18 q ck d s q ck d s q i 19 q ck d s q ck d s q h 20 q ck d s q ck d s q g 21 q ck d s q ck d s q f 22 q ck d s q ck d s q e 23 q ck d s q ck d s q d 24 q ck d s q ck d s q c oe enable input 5 s 4 s 8 7 6 gnd 9 s s s 10 sq p 2 q ck d s q ck d s q b 1 q ck d s q ck d s q a vcc 3 a serial data input ck s shift clock input ck l latch clock input r direct reset input serial data output parallel data outputs logic diagram serial data output sq p output format parallel data outputs q a ? q p data signal oe signal 12 q ck d s q ck d s q p 12 q ck d s q ck d s q p q p 11 q ck d s q ck d s q o 11 q ck d s q ck d s q o q o 13 q ck d s q ck d s q n 13 q ck d s q ck d s q n q n 14 q ck d s q ck d s q m 14 q ck d s q ck d s q m q m 15 q ck d s q ck d s q l 15 q ck d s q ck d s q l q l 16 q ck d s q ck d s q k 16 q ck d s q ck d s q k q k 17 q ck d s q ck d s q j 17 q ck d s q ck d s q j q j 18 q ck d s q ck d s q i 18 q ck d s q ck d s q i q i 19 q ck d s q ck d s q h 19 q ck d s q ck d s q h q h 20 q ck d s q ck d s q g 20 q ck d s q ck d s q g q g 21 q ck d s q ck d s q f 21 q ck d s q ck d s q f q f 22 q ck d s q ck d s q e 22 q ck d s q ck d s q e q e 23 q ck d s q ck d s q d 23 q ck d s q ck d s q d q d 24 q ck d s q ck d s q c 24 q ck d s q ck d s q c q c oe enable input 5 5 s s s 4 4 s s s 8 8 7 7 6 6 gnd 9 gnd 9 9 s s s s s s s s 10 sq p 2 q ck d s q ck d s q b 2 q ck d s q ck d s q b q b 1 q ck d s q ck d s q a 1 q ck d s q ck d s q a q a vcc 3 vcc 3 3
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 2 of 7 pin configuration ( top view ) functional description as r8a66161 uses silicon gate cmos process. it rea lizes high-speed and high-output currents sufficient for led drive while maintaining low power consumption and allowance for high noises. each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. as for clock input, shift clock input ck s and latch clock input ck l are independent from each other, shift and latch operations being made when ?l? changes to ?h?. serial data input a is the data input of the first-step shift register and the signal of a shifts shifting registers one by one when a pulse is impressed to ck s . when a is ?h?, the signal of ?l? shifts. when the pulse is impressed to ck l , the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from q a ~ q p . outputs q a ~ q p are open drain outputs. to extend the number of bits, use the serial data output sq p which shows the output of the shifting register of the 16th bit. when reset input r is changed to ?l?, q a ~ q p and sq p are reset. in this case, shifting and latching register are set. if ?h? is impressed to output enable input oe, q a ~ q p reaches the high impedance state, but sq p does not reach the high impedance state. furthermore, c hange in oe does not affect shift operation. function table (note: 1) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 qa qb a oe ckl r cks sqp qo qp qc qd qe qf qg qh qi qj qk ql qm qn a ck l ck s sq p q c q d q e q f q g q h q i q j q k q l q m q n parallel data outputs serial data input enable input latch clock input direct reset input shift clock input serial data output parallel data outputs parallel data outputs v cc gnd q a q b oe r q o q p 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 qa qb a oe ckl r cks sqp qo qp qc qd qe qf qg qh qi qj qk ql qm qn a ck l ck s sq p q c q d q e q f q g q h q i q j q k q l q m q n parallel data outputs serial data input enable input latch clock input direct reset input shift clock input serial data output parallel data outputs parallel data outputs v cc gnd q a q a q b q b oe oe r r q o q o q p q p : change from low-level to high-level : output state q before ck l changed : irrelevant : contents of shift register before ck s changed : contents of shift register : t 2 is set after t 1 is set : high impedance note1: a q x q q t 1 , t 2 z 0 0 operation mode shift latch operation input parallel data output ck s ck l a r oe q a q b q c q d q e q f q g q h q i q j q k q l q m q n q o q p serial data output sq p remarks shift t 1 h a xhl q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl l q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 shift t 1 h a xll q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl z q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 reset lxxxxzzzzzzzzzzzzzzzzl output lighting l h z output disable xxxxh z zzz zz zzzz zzz zz z q p output lights-out l l z : change from low-level to high-level : output state q before ck l changed : irrelevant : contents of shift register before ck s changed : contents of shift register : t 2 is set after t 1 is set : high impedance note1: a q x q q t 1 , t 2 z 0 0 : change from low-level to high-level : output state q before ck l changed : irrelevant : contents of shift register before ck s changed : contents of shift register : t 2 is set after t 1 is set : high impedance note1: a q x q q t 1 , t 2 z 0 0 operation mode shift latch operation input parallel data output ck s ck l a r oe q a q b q c q d q e q f q g q h q i q j q k q l q m q n q o q p serial data output sq p remarks shift t 1 h a xhl q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl l q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 shift t 1 h a xll q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl z q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 reset lxxxxzzzzzzzzzzzzzzzzl output lighting l h z output disable xxxxh z zzz zz zzzz zzz zz z q p output lights-out l l z operation mode shift latch operation input parallel data output ck s ck l a r oe q a q b q c q d q e q f q g q h q i q j q k q l q m q n q o q p serial data output sq p remarks shift t 1 h a xhl q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl l q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 shift t 1 h a xll q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q p 0 q o 0 latch t 2 hx a xl z q a 0 q b 0 q c 0 q d 0 q e 0 q f 0 q g 0 q h 0 q i 0 q j 0 q k 0 q l 0 q m 0 q n 0 q o 0 q o 0 reset lxxxxzzzzzzzzzzzzzzzzl output lighting l h z output disable xxxxh z zzz zz zzzz zzz zz z q p output lights-out l l z
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 3 of 7 absolute maximum ratings (ta=-40~+85 ? , unless otherwise noted) symbol parameter conditions ratings unit v cc supply voltage -0.5 ~ +7.0 v v i input voltage -0.5 ~ v cc +0.5 v v o output voltage -0.5 ~ v cc +0.5 v q a ~ q p 50 i o output current per output pin sq p 25 ma i cc supply / gnd current v cc , gnd -20, +410 ma p d power dissipation (note 2) 500 mw t stg storage temperature range -65 ~+150 ? note 2: R8A66161SP; ta=-40 ? +70 ? , ta=+70 ? +85 ? are derated at -6mw/ ? . recommended operating conditions (ta=-40~+85 ? , unless otherwise noted) limits symbol parameter min. typ. max. unit 5.0v support 4.5 5.0 5.5 v v cc supply voltage 3.3v support 3.0 3.3 3.6 v v i input voltage 0 v cc v v o output voltage 0 v cc v t opr operating temperature range -40 +85 ?
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 4 of 7 electrical characteristics 5.0v version support specifications (ta=-40~+85 o c,vcc=4.5v~5.5v, unless otherwise noted) limits symbol parameter test conditions min. typ. max. unit v t+ positive-going threshold voltage v o =0.1v, v cc -0.1v |i o |=20ua 0.35xv cc 0.70xv cc v v t- negative-going threshold voltage v o =0.1v, v cc -0.1v |i o |=20ua 0.20xv cc 0.55xv cc v i ol = 20ua 0.10 v i =v t+ ,v t- v cc =4.5v i ol = 24ma 0.53 v ol low-level output voltage q a ~ q p (note3) i ol = 40ma 0.94 v i oh = -20ua v cc- 0.1 v oh high-level output voltage sq p v i =v t+ ,v t- v cc =4.5v i oh = -4ma 3.66 v i ol = 20ua 0.10 v ol low-level output voltage sq p v i =v t+ ,v t- v cc =4.5v i ol = 4ma 0.53 v i ih high-level input current v i =v cc , v cc =5.5v 5 ua i il low-level input current v i =gnd, v cc =5.5v -5 ua v o =v cc 10 i o maximum output leakage current q a ~ q p v i =v t+ ,v t- v cc =5.5v v o =gnd -10 ua i cc quiescent supply current v i =v cc ,gnd, v cc =5.5v 200 ua note 3: r8a66161 is used under the condition of an output current i ol =40ma, the number of simultaneous drive outputs is restricted as shown in the duty cycle ? i ol of typical characteristics. 3.3v version support specifications (ta=-40~+85 o c,vcc=3.0v~3.6v, unless otherwise noted) limits symbol parameter test conditions min. typ. max. unit v t+ positive-going threshold voltage v o =0.1v, v cc -0.1v |i o |=20ua 0.35xv cc 0.70xv cc v v t- negative-going threshold voltage v o =0.1v, v cc -0.1v |i o |=20ua 0.20xv cc 0.55xv cc v i ol = 20ua 0.10 v i =v t+ ,v t- v cc =3.0v i ol = 12ma 0.54 vv ol low-level output voltage q a ~ q p i ol = 20ma 0.72 v i oh = -20ua v cc- 0.1 v oh high-level output voltage sq p v i =v t+ ,v t- v cc =3.0v i oh = -2ma 2.60 v i ol = 20ua 0.10 v ol low-level output voltage sq p v i =v t+ ,v t- v cc =3.0v i ol = 2ma 0.40 v i ih high-level input current v i =v cc , v cc =3.6v 5 ua i il low-level input current v i =gnd, v cc =3.6v -5 ua v o =v cc 10 i o maximum output leakage current q a ~ q p v i =v t+ ,v t- v cc =3.6v v o =gnd -10 ua i cc quiescent supply current v i =v cc ,gnd, v cc =3.6v 200 ua
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 5 of 7 switching characteristics (ta=-40~+85 o c,vcc=5.0v or 3.3v) 5.0v specification 3.3v specification symbol parameter te s t conditions min. typ. max. min. typ. max. unit f max maximum clock frequency 4 3.3 mhz t plh 125 150 ns t phl output ?l?-?h? and ?h?-?l? propagation time ck s - sq p 125 150 ns t phl output ?h?-?l? propagation time r ? sq p 125 150 ns t plz output ?l?-?z? propagation time r - q a ~ q p (turned off) 200 220 ns t pzl output ?z?-?l? propagation time ck l - q a ~ q p (turned on) 125 150 ns t plz output ?l?-?z? propagation time ck l - q a ~ q p (turned off) 200 220 ns t pzl output ?z?-?l? propagation time oe - q a ~ q p (turned on) 125 150 ns t plz output ?l?-?z? propagation time oe - q a ~ q p (turned off) c l =50pf r l =1k ? (note 4) 200 220 ns c i input capacitance 10 10 pf timing requirements (ta=-40~+85 o c,vcc=5.0v or 3.3v) 5.0v specification 3.3v specification symbol parameter te s t conditions min. typ. max. min. typ. max. unit t w ck s , ck l , r pulse width 125 150 ns t su a setup time with respect to ck s 125 150 ns t su ck s setup time with respect to ck l 125 150 ns t h a hold time with respect to ck s 15 20 ns t rec r recovery time with respect to ck s , ck l (note 4) 70 80 ns note 4 : test circuit pg gnd 50
input v cc c l sq p (1) the pulse generator (pg) has the following characteristics (10%~90%). :tr = 6ns, tf = 6ns. (2) the capacitance c l includes stray wiring capacitance and the probe input capacitance. r l v cc c l q a ? q p dut note 4 : test circuit pg gnd 50
input v cc c l sq p c l sq p (1) the pulse generator (pg) has the following characteristics (10%~90%). :tr = 6ns, tf = 6ns. (2) the capacitance c l includes stray wiring capacitance and the probe input capacitance. r l v cc c l q a ? q p r l v cc c l q a ? q p dut
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 6 of 7 typical characteristics from top to bottom duty cycle-i ol characteristics i ol (ma) i ol (ma) duty cycle (%) duty cycle (%) vcc=4.5v, ta 1 85 ? vcc=4.5v, ta 1 25 ? 0 20 40 60 80 100 duty cycle-i ol characteristics timing diagram ~ ~ ~ repetition frequency > 10 hz numbers in indicate the number of output circuits that operate simultaneously. current values are per circuit. ck s sq p t w 50% 50% 50% t plh t phl 50% 50% v cc gnd v oh v ol 50% 50% oe 50% 10% t pzl t plz v ol v cc gnd ck l 50% t pzl t plz 50% 10% v cc gnd v ol v ol 50% 50% t su t h 50% ck s a v cc gnd v cc gnd 50% ck l ck s 50% 50% t su t w v cc gnd v cc gnd ck s sq p q a ? q p 50% 50% 50% 50% 10% v cc gnd v oh v ol v cc gnd v ol r t w t rec t phl t plz q a ? q p q a ? q p q a ? q p ck s sq p t w 50% 50% 50% t plh t phl 50% 50% v cc gnd v oh v ol 50% 50% oe 50% 10% t pzl t plz v ol v cc gnd ck l 50% t pzl t plz 50% 10% v cc gnd v ol v ol 50% 50% t su t h 50% ck s a v cc gnd v cc gnd 50% ck l ck s 50% 50% t su t w v cc gnd v cc gnd ck s sq p q a ? q p 50% 50% 50% 50% 10% v cc gnd v oh v ol v cc gnd v ol r t w t rec t phl t plz q a ? q p q a ? q p q a ? q p
r8a66161dd/sp rej03f0262-0100 rev.1.00 jan.16.2008 page 7 of 7 package outline product name package renesas code previous code r8a66161dd 24pin dip prdp0024af-a 24p4x-a R8A66161SP 24pin sop prsp0024df-a 24p2x-b all trademarks and registered trademarks are th e property of their respective owners.
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